1. Field of the Invention
This invention generally relates to electronic circuitry and, more particularly, to a system and method for deterministic jitter-free fractional division.
2. Description of the Related Art
FIG. 1 is a schematic block diagram of a conventional phase locked loop (prior art). A phase detector (or frequency detector) receives a first input signal, such as might be supplied on a serial data stream or a clock source, and compares it to a second input signal supplied by the divider. The phase detector (PD) generates an output that is responsive to difference in timing between the two input signals. A charge-pump may be added to improve the response of the PLL, as the phase detector output does not necessarily have enough drive to instantaneously charge (or discharge) the loop filter reactances. The loop filter is typically a low-pass filter, and is used to control the overall loop response. The voltage controlled oscillator (VCO) supplies an output frequency that is responsive to the input voltage level. The loop is locked when the phase detector inputs match. The divider is typically inserted in the path between the VCO and the phase detector. The divider has two primary functions. The divider permits the phase detector to be operated at a lower frequency. Also, the divider acts as a relatively simple means of controlling the VCO output frequency.
The VCO can be controlled to supply a number of different frequencies by manipulating the division ratio. This task is relatively simple if the divider is a hardware device designed to divide the VCO frequency by a range of selectable integer numbers. “Pulse-swallowing” is one technique that can be used to obtain a desired division ratio. Pulse-swallowing also permits non-integer and odd-inter ratios to be obtained. For example, a divisor of 3 may be obtained if the VCO frequency is alternately divided by the divisors of 2 and 4. However, the pulse-swallowing technique may generate undesirable harmonic frequencies components and pulse jitter. Further, it may not be possible to conveniently generate every required frequency using just the pulse-swallowing technique.
FIG. 2 is a timing diagram depicting a fractional clock output with jitter (prior art). The period of the output clock is equal to the input clock divided by 2.25. For the (N+0.25) divide ratio where N=2, the divider divides input clock by N(2) for 3 cycles, then divides the input clock by N+1(3) for one cycle. The total divide ratio is ((3×N)+(N+1))/4=N+0.25. The average period, or combination of the output clocks is equal to the input clock/2.25. However, the jitter can be as large as one input clock period. Jitter, as defined herein, is a periodic waveform asymmetry or spurious frequency component associated with an intended frequency. Glitch is defined as a random unintended signal.
FIG. 15 depicts a drawing from pending parent application entitled, HIGH SPEED MULTI-MODULUS PRESCALAR DIVIDER, invented by An et al., Ser. No. 11/717,261, filed Mar. 13, 2007. This application discloses a divider capable of dividing a clock frequency by a integer, without resorting to pulse-swallowing. The divider enables the division process by generating a plurality of clock phase and uses a counter to select clock phases. While the divider is capable of creating each output clock period accurately, the selection of phase inputs by the MUX is not always free of glitches.
It would be advantageous if a divider existed that was able to divide an input clock within a range of selectable values and create a jitter-free output clock.